MEPTEC, the MicroElectronics Packaging and Test Engineering Council, is pleased to announce the addition of a 30 year veteran of the semiconductor industry, William Bottoms, Ph.D., as keynote speaker for its next one-day technical symposium “IC Packaging & Test Roadmaps: Device Trends Impact on Packaging & Test Technology and Supply Chain.”  The event will be held on November 16, 2006 at the Holiday Inn San Jose (formerly Hyatt San Jose) in San Jose, CA.

Dr. Bottoms is currently Chairman and CEO of NanoNexus, Inc. which provides advanced contactor and interconnect products to the electronics industry.  Bottoms is also currently chairman of the technology working group for Assembly and Packaging of the International Technology Roadmaps for Semiconductors (ITRS).  He has also chaired a number of government committees that set technology roadmaps and direction including the National Research Council Board on Assessment of NIST programs.

According to Dr. Bottoms, there are several large electronics industry Roadmap activities including ITRS, JISSO and iNEMI and they all share one basic element.  The transistor is no longer the limiting factor in cost or performance of electronic products. Moore’s law scaling is nearing its end and assembly and packaging innovation is taking up the slack. New materials, new architectures and innovation in packaging and interconnect technologies are emerging. Driven by a consumer dominated industry, assembly and packaging innovation will make a greater contribution to progress over the next decade than IC innovation. In his keynote presentation, Mr. Bottoms will share his views of how this progress, supported and enabled by the Roadmap activities and the industry wide cooperation they represent, is a foundation of our continued technical progress and growth.

In addition to the keynote presentation, the program has been segmented into the following focus areas with presentations provided by major areas of the semiconductor industry:

Packaging Challenges for Semiconductor Devices – Device manufacturers will discuss:

• How long will it take before electrical performance is compromised for thermal efficiency
• Can one package style continue to be dominant for a particular device family
• With a cost-conscious, short product life-cycle of the consumer market now driving the industry forward, does long-term reliability take a back seat to the “throw-it-away, I want a new one” mentality
• Are companies packaging roadmaps really compatible with customer’s system or product goals

Converging and Diverging Packaging Roadmaps – In this session subcon assemblers will focus on the rapid changes in assembly and packaging underway today and the Roadmaps for continued innovation. Assembly and packaging innovation is essential and it is underway at an unprecedented rate.  This session will address three of the most significant areas of innovation today representing the divergence driven by consumer product demands and the convergence driven by the requirement for lower cost system level integration.

Test Challenges, Trends and Roadmaps – This session will focus on how semiconductor test is changing to meet the demands of the migration of test capability for testing multiple technologies in one platform, the impact of new package technology on handler systems and discuss new trends in the areas of Open Architecture.

Semiconductor Manufacturing Supply Chain Trends and Roadmaps - In this session, panelists representing all segments of the industry will be present to answer questions on Supply Chain Management and the emergence of a Full Service Marketplace. From Fabless Semiconductor Manufacturing to SAT to Automatic Test Equipment (ATE) Manufacturing to EMS, we will hear the opinions and decisions behind the systems that keep our orders fulfilled.

To register for or learn more about the symposium, please contact Bette Cooper at 650-714-1570 or bcooper@meptec.org or visit MEPTEC at www.meptec.org.