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IWLPC workshops by experts cover timely semiconductor packaging topics Imprimir E-Mail

Four experts in integrated circuit packaging will offer half-day workshops at the International Wafer-Level Packaging Conference (IWLPC) on November 1, the kickoff day for the conference.

Workshops include "The Reliability of Wafer-Level CSP," headed by Dr. John H. Lau; "Development, Deployment and Accelerating 3D Wafer-Level CSP," instructed by Dr. Daniel F. Baldwin; "3D Packaging Applications, Requirements, Infrastructure, and Technologies," with Lee Smith; and "After the Wafer: An Overview of Post-Wafer-Level Packaging Support Infrastructure" led by Joseph C. Fjelstad.

Dr. Lau is the author or co-author of several books on semiconductor packaging, including Chip Scale Packages, Electronic Packaging, and Low Cost Flip Chip Technologies. He earned a doctorate in theoretical and applied mechanics from the University of Illinois and currently serves with Agilent Technologies.

Dr. Baldwin is an associate professor of mechanical engineering at Georgia Tech’s Packaging Research Center and the founder of Engent Inc., a company specializing in enabling process technologies and manufacturing services in electronics, optoelectronics and MEMS. He received a doctorate in mechanical engineering from MIT.

Lee Smith of Amkor Technology Inc. is a recognized industry expert in semiconductor packaging, with more than 25 years of cross-market experience. Over the past 10 years he has been directly involved in 3D packaging at Amkor, Tessera and Texas Instruments. While at TI, he was chartered with defining, developing and deploying package-on-package technology.

Joe Fjelstad is one of the industry’s most prolific authors and lecturers on emerging IC packaging technologies, chip-scale packages and flexible circuits. He is the author or co-author of several books on packaging including Chip Scale Packaging for Modern Electronics and An Engineer’s Guide to Flexible Circuit Technology. He is also the founder of Silicon Pipe Inc. and was Tessera’s first corporate Fellow.

The IWLPC, co-presented by Chip Scale Review and the SMTA, will take place November 1-3 at the Wyndham Hotel in San Jose. The two days following the workshops will be devoted to technical presentations, panels and exhibits by industry vendors.

More information and online registration is available at www.smta.org/iwlpc.

 

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