Effect of Voids on Thermo- Mechanical Reliability of Solder Joints

BY MORGANA RIBAS, PH.D., SIULI SARKAR, PH.D., ALPHA ASSEMBLY SOLUTIONS, MACDERMID
PERFORMANCE SOLUTIONS ALPHA INDIA R&D CENTRE, BANGALORE, KA, INDIA, CARL BILGRIEN, PH.D., TOM
HUNSINGER, ALPHA ASSEMBLY SOLUTIONS, SOMERSET, NJ USA

Read more: Global SMT & Packaging Magazine Volume 18 • Number 10 • October 2018 • ISSN 1474 –0893

Despite being a continuous subject of discussion, the existence of voids and their effect on solder joint reliability has always been controversial. In this work we revisit previous works on the various types of voids, their origins and their effect on thermo-mechanical properties of solder joints. We focus on macro voids, intermetallics micro voids, and shrinkage voids, which result from solder paste and alloy characteristics. We compare results from the literature to our own experimental data, and use fatigue-crack initiation and propagation theory to support our findings. Through a series of examples, we show that size and location of macro voids are not the primary factor affecting solder joint mechanical and thermal fatigue life. Indeed, we observe that when these voids area conforms to the IPC-A610 (D or F) or IPC-7095A standards, macro voids do not have any significant effect on thermal cycling or drop shock performance. could support (or not) voids as points of stress for crack initiation and growth. Therefore, we start this work by reviewing the related literature and discussing these two topics in more details.

One of the early studies trying to understand the effect of voids on BGA/CSP solder joints fatigue life concluded on some sort of relation between voids and lower thermal cycling performance.4 In another early study based on finite element method analysis, equivalent plastic strain and shear strain of solder joints with voids of various sizes at different positions were calculated.5 It concluded that presence of voids does not always have a negative effect on thermal fatigue of the solder joints. Later on, several other experimental and theoretical studies made similar suggestions that thermal fatigue is mostly not affected by the amount of voids in the solder joint. Some of these studies are also reviewed here when discussing the relationships between voids and the solder joint thermal and mechanical reliability.

Failures in electronic components during thermal cycling occur due to thermal stresses in solder joints. These thermal stresses can reduce the solder joint fatigue life, depending on the mechanical reliability of these solder joints. Thus, we compare thermal cycling or drop shock performance of individual solder joints with their respective cross-section appearance. We present various examples taken from our work on Sn-Ag-Cu Pb-free alloys, in which the voids conform to the IPC-A-610 standard (revisions D or F) and reflect actual processing conditions, and compare with the findings in the literature. Finally, we discuss how our experimental data can be viewed in light of fracture mechanics theory for crack initiation and growth.

Voids and cracks
Very good descriptions of the various types of voids can be found in the literature, such as the references cited here.6-9 Basically, voids can be divided in six categories:

  • Macro Voids: Very common type of voids as they are generated, mostly, by the evolution of volatiles from the paste flux during reflow. Also known as process voids.
  • Intermetallics (IMC) Micro Voids or Kirkendall Voids: Located between the intermetallic layer and the copper substrate. Caused by differences in diffusion rates between Cu and Sn.
  • Shrinkage Voids: Unique to Pb-free alloys, these are caused by contraction stresses on solidifying interdendritic eutectic solder.
  • Planar Micro Voids: Also called “champagne” voids, are generally smaller than 25 µm. Can occur during various steps in surface finish platting.
  • Micro-via Voids: Not unique to Pb-free alloys. Caused by

Introduction
Son this subject, including several industry consortiums ince the introduction of near eutectic lead-free alloys in the early 2000’s, there was a concern on increased number of voids during the reflow process when compared to eutectic Sn-Pb solder. There have been numerous studies and standards development dedicated to address this issue.1-3 Whereas some believe that voids will act as stress concentrators, reducing the solder joint fatigue life, others suppose exactly the opposite, that voids can act as stress relief to reduce the speed of crack propagation. Failures of electronic components undergoing thermal cycling occur due to thermal stresses in solder joints. Depending on the mechanical reliability of these solder joints, these thermal stresses can somehow reduce the solder joint fatigue life. Prior to starting any further discussion on voids, it is important to distinguish the various types of voids. Some voids result from very specific choices of solder alloys or materials used in the printed circuit board (PCB) design, whereas others are inherent to the surface mount technology (SMT) process. However, no discussion would be complete without further investigation on how fracture mechanics theories.

Read more: Global SMT & Packaging Magazine Volume 18 • Number 10 • October 2018 • ISSN 1474 –0893

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