The Impact of Plated Layer Contamination on Semiconductor Assembly: A Failure Analysis Perspective
In the world of both package and board level assembly, the pads on ceramic substrates, laminate substrates or PBC boards are metallized using either electrolytic or electroless plating.
Plating is a solution based, sequential process where Cu plating may be followed by Ni or Ni/ Pd and finally Au or Ag. Each plating process is separated by rinses, but the plating sequence is in one continuous plating line. The propensity for liquids to be carried by the plated substrates and racks upstream carries a high potential for contamination of upstream plating baths. In addition, the highly corrosive environment of a plating line means that chemical attack of metallic plating racks and other equipment in the line is always present. These corrosion products also end up in plating baths and thus in plated layers.
Chemicals critical to plating bath construction also present sources of ionic contamination. For example, electrolytic Ni plating baths typically contain anions SO4- and Cl- as well as cation H+. These ions can end up on the surface of plated parts, or gases evolved during plating such as H2 can be absorbed by growing plated layers.
Long chain organic molecules are also added to plating baths to control deposition uniformity, grain size as well as surface texture (Brighteners, Levelers). With usage, these long chain molecules will break down into short chain fragments, and these fragments will then end up being incorporated into the plated layer. This organic contamination of the plated layer will influence the layers chemical and mechanical properties, which in turn will impact assembly processes.
This paper will consider the impact of various aspects of plated pad contamination from a Failure Analysis perspective. For each case, we will present the observed failure mode and the analysis that was done to trace the failure to a specific plated layer contamination process. We will also discuss how the failure mode can be eliminated by increasing control of the plating process or altering some aspect of the assembly process. From an assembly perspective, the focus will be on die attach and wirebonding processes.
Organic contamination of plated Au pads resulting in non-stick Al wirebonds
During Al wirebonding to Au pads on a ceramic package more than 5% of the Al wires did not bond to the pads (“non-sticks”). These non-stick wires were observed to lift off of the pads after the wirebonding process. The pad metallization was tungsten with electrolytically plated Ni (4 μm) and Au (3 μm). An SEM based investigation was initiated to determine the root-cause of the non-stick wirebonds.
Wirebond pads for both PCB and ceramic substrates are frequently coated with electrolytic Ni and electrolytic Au. For bonding of Al wire, this Au layer actively participates in bond formation through the formation of Au-Al intermetallic compounds which act as the bonding phase. For successful bonding phase formation, very high purity, soft Au is required to first form an intimate interface between the Al wire and the Au pad, a precursor to formation of the AuAl IMC phases.
As mentioned in the introduction, organic additives are critical components of Au plating baths and play a number of beneficial functions. Organic additives act to level out the plated layer so that high current density features such as edges and corners can be plated with the same layer thickness as the rest of the surface. Organic additives also impact Au grain size and texture which impacts surface finish.
Organic additives act to level out the plated layer so that high current density features such as edges and corners can be plated with the same layer thickness as the rest of the surface.
Though organic additives are beneficial, over time they will break down from long-chain useful molecules to short-chain organic fragments which plated layer. When this happens, the Au layer becomes harder and more porous. This trend of organic contamination induced hardness will increase with bath age as more organic additives breakdown to form fragments that are then incorporated into the plated layer. This trend is shown in Figure 1. Over 30 days of bath usage, the hardness of the deposit from a cyanide Au bath is seen to monotonically increase.
In the case shown in Figure 1, after 30 days all of the organics from the Au bath were removed using an activated carbon filtration process. After this treatment, the bath was replenished with a new package of organic additives and hardness was-re-measured. After carbon filtration of the short chain organic contamination, the hardness of the deposit is observed to return back to the “fresh bath” level near 70 Hv.
For an aged Au bath, both the hardness and high organic surface content can have a very serious impact on the wirebonding process.
Figure 2(a) is the Au pad from the ceramic package that failed wirebonding in the example above. Note the grains are very small (<1 μm) and there is a high level of porosity in the plated layer. The porosity is a strong indicator of high organic content. Both organic contamination and small grain size lead to hard Au deposits. Micro-hardness testing showed a hardness value > 100Hv, significantly harder than Au plated from a fresh bath which had a hardness near 70 Hv. Figure 2(b) shows the microstructure of dense, soft Au that is ideal for wirebonding.
As shown in Figure 1, when the bath that created the hard, porous, fine grain Au deposit shown in Figure 2(a) was treated with activated carbon and the plating current density was lowered, the hardness returned to levels below 80 H. In addition, the deposit became dense and the grain size increased to the 2-5 μm range. After these adjustment, the Al wirebonding non-stick issues were eliminated.
Metallic impurity induced voiding in AuAl wirebonds
An Al wire bonded to a Au pad on a power device failed after burn-in. A cross section of both the wire “foot” (originally bonded segment of the wire) and the pad were prepared. Figure 3 shows a transverse cross section of the failed wire foot at low magnification, and Figure 4 shows the IMC phases at higher magnification. These cross sections show that the failure occurred between the Au pad and a Au-rich AuAl IMC phase.
To further determine the root cause of this failure, Auger analysis was done on the Au pad to look with high sensitivity for impurities which might influence the wirebond process. The Auger spectra was taken on a corner of the pad which was not impacted by the wirebond process. The Auger spectra, which is shown in Figure 5, shows a high level of Ni impurity on the Au pad.
Horsting1 examined the impact of metallic impurities in Au during AuAl wirebonding. Horsting showed that when the Au pad reacts with Al wire to form AuAl IMC phases, impurities in the Au will concentrate at the AuAl reaction front. These concentrated impurities then act as sinks for vacancy formation. Vacancies localized along an interface, particularly at elevated temperature during burn in, can coalesce to form voids along the interface which eventually leads to bond failure. This type of voiding is seen in highly Au rich IMC phases near the Au interface, as observed here.
So one key question- what is the source for Ni impurities in plated Au?
There are two potential mechanisms for a plated Au pad to be contaminated with Ni.
Since the nickel plating bath is an adjacent, down-stream process to Au plating, separated only by rinse tanks, a phenomena called “drag-out” can occur. Drag-out refers to Ni plating solution that was not completely rinsed off of boards or was trapped in occluded areas of the plating rack which then contaminates the upstream Au bath. Once Ni enters the Au bath, it can co-plate with the Au. Drag-out issues can be remedied by enhanced rinse and by re-design or maintenance of plating racks to reduce areas that can trap solution.
The second mechanism for Ni contamination of Au plated layers does not occur during plating but occurs during subsequent thermal processes such as die attach.
The second mechanism for Ni contamination of Au plated layers does not occur during plating but occurs during subsequent thermal processes such as die attach.
Though Ni diffusion through Au grains is very slow, Ni can rapidly diffuse into the Au layer along grain boundaries. The bulk and grain boundary diffusion coefficient of Ni in Au is shown in Figure 5.2 You can see the grain boundary diffusion of Ni in Au is as much as 6 orders of magnitude higher than bulk grain diffusion. The amount of Ni that diffuses to the Au surface will depend strongly on two factors. The first factor is Au thickness. The second factor is time at elevated temperature during any process step between Au plating and wirebonding. For typical Au thickness between 1 and 2 microns, temperature in the range of 250C or above are required to result in any significant Ni diffusion to the Au surface.
AuSn die attach and blister screen operations are potential sources for diffusion related Ni contamination of Au. The key to avoiding this issue is to limit time for processes above 250C prior to wirebonding.
In the failure analysis case discussed above for AuAl bonding, Ni contamination of the Au plated layer resulted in void formation as proposed by Horsting. Ni on the surface of a plated Au pad can also have a very significant impact for Au-Au wirebonds. Figure 73 shows Au wirebond non-stick incidence as a function of Ni concentration on plated Au.
In this case, the proposed failure mechanism is due to formation of Ni oxide on the pad surface. The Ni oxide layer prevents intimate contact between the Au wire and Au pads, preventing formation of a Au-Au diffusion bond between the wire and pad.
Plating nodules and die attach voiding
For high thermal or electrical demand applications, there is a strong trend toward decreasing die attach layer thickness to produce bond line thicknesses < 10 μm. This is true for both AuSn hard solder die attach and Ag filled epoxy. The advantage of thinner bond lines is both decreased die attach material cost (very key for AuSn) and also decreased thermal and electrical resistance.
Impurities or foreign material in a plating bath, particularly for Cu and Ag plating, can result in the formation of a nodular structure on the surface of the plated pad. If this nodular structure becomes larger than a few microns, it can result in significant voiding for thin bond line thicknesses.
Cu plating – sources for nodule formation
Most nodules in a Cu plated layer form as a result of foreign material or particles in the plating bath. Since baths are continuously filtered, the particles that create the most serious issue are those that are produced as a result of the plating process itself.
There are two critical sources of particulate contamination for electrolytic Cu. Many electrolytic Cu plating baths use “soluble anodes” as a source of Cu ions. Soluble anodes are balls of CuP, contained in a Ti cage, that are anodically biased during the plating process. During plating, these balls dissolve in the H2SO4 electrolyte forming Cu2+ and SO42- ions in solution. The Cu2+ ions then plate out on the cathodically biased substrate.
The CuP balls, however, do not dissolve completely. As they get smaller and smaller they start to loose electrical contact with adjacent balls and the Ti cage. Even though there is a filter bag around the whole anode, as these particles disintegrate, small Cu particles escape into the bath. When these particles come into the vicinity of the cathode, they become incorporated into the plated layer. As plating proceeds on top of these entrapped particles a nodule is formed.
Figure 8 shows a cross section of a Cu nodule on the surface of a Cu/Ni/Au plated pad. This cross section was etched to show the Cu grain structure. After etching, a spherical Cu particle is seen as the source of the nodule. As above, this nodule adhered to the Cu surface during plating and was subsequently plated over as Cu plating proceeded.
A second source of foreign material in a Cu plating bath comes from the electrical contacts on the plating rack. For electrolytic plating, each substrate must be electrically contacted by the plating rack. During the plating process, the contacts on the rack will plate along with the pads on the substrate.
Because the contacts are generally a wire or pin, plating near the pin tip region will become very thick due to very high current densities around sharp features. This thick plated Cu on a plating rack contact tip often results in formation of Cu flakes, which can sluff off and end up in the plating bath. Just as in the case of Cu anode disintegration, these flakes can be come incorporated in the plated layer resulting in nodule formation.
Plated under-layer oxidation
A lead-frame that was plated with electroless Ni and immersion Au (ENIG) had very poor SAC305 solder wetting. To analyze the root cause of this issue, the ENIG plated pad was cross-sectioned and examined in an SEM. Figure 9 below shows the structure of the plated layers.
What this figure shows is severe corrosion of the electro-less NiP layer by the immersion Au plating solution. It is evident that this corrosion was caused during the immersion Au deposition because the corroded NiP areas (now Ni-oxide) are also filled with plated Au.
This is a well-documented phenomena called “black pad”. During soldering, the Au layer is dissolved by the SAC 305 solder which exposes the oxidized Ni layer. Once the liquid solder hits the oxide surface it will de-wet from the pad. While the solder is interacting with the Au layer, it will wet across the whole
surface. When this wetted layer then de-wets, it forms small beads of solder across the surface of the pad.
One well known solution to avoid this problem is to introduce a Pd layer between the electroless plated Ni and the Au: electroless Ni, immersion Pd, immersion Au (ENIPIG). The Pd layer protects the electroless NiP from the immersion Au plating chemistry during the plating process.
One significant issue, however with Pd in the plated layer stack up is that solder voids become much more stable when Pd is one of the pad metal layers. Solder voids are generally caused by solder flux that vaporizes during the soldering process and cannot escape from the liquid solder layer. Figure 10 shows SAC305 solder with a solder void and the intermetallic structure that can occur when Pd is present.
Note that there is a (Pd,Ni)Sn IMC phase which forms around the void (the rest of the structure in the micrograph is Sn). This phase likely precipitates out of the liquid solder around the perimeter of the void. It is very likely that the formation of this precipitated and solidified (Pd,Ni)Sn phase around the perimeter of the void serves to stabilize the void, making it much more difficult for the trapped gas to escape through the liquid solder. This type of structure is not seen when soldering to plated layers with no Pd.
This analysis shows that the thickness of Pd in ENIPIG plating is very critical. Too thin and black pad associated solder de-wetting can occur. Too thick, and solder void stabilizing (Pd,Ni)Sn phase can form.
Contamination within the plated layer stack
A RF power amplifier was mounted on a Cu/W flange that was plated with Ni and Au. After AuSi die attach at 420C, blisters were observed on the surface of the plated flange. In order to determine the root cause of the blister formation, one of the blisters was opened up and both sides of the de-lamination failure were examined in an SEM with EDS. Figure 11 shows the peel blisters surfaces in optical and SEM images.
Figure 12 shows EDS analysis of underside of the peel metal.
Both the underside and top side of the failure interface showed predominantly Ni, indicating that the failure occurred between two different plated Ni layers.
During the flange plating process, first a Ni strike layer is deposited. This layer is plated from a very high Ni concentration bath at very high current density. The purpose of the Ni strike is to get good adhesion to the Cu/W flange surface. After the Ni strike is deposited, the flange goes into a new Ni bath where a thicker Ni layer is deposited at lower current density. The chemical analysis of the two sides of the failure show that the failure occurred between the Ni strike and Ni plated layers.
The EDS spectra also shows high levels of Cu on both sides of the failure. On the top surface, the Cu layer was 15.5 at.% (shown) and on the bottom layer 39 at.% (not shown). This Cu contamination is very likely the root cause of the Ni to Ni delamination which
results in the formation of the observed blister.
Since the Cu/W flanges go directly into the Ni strike bath after cleaning, the most likely bath to be contaminated with high levels of Cu is the strike bath. For this reason, Ni strike baths must be constantly monitored for build-up of contamination. When Cu levels exceed 20 ppm, the bath should be replaced.
If Cu is present on the surface of the Ni strike layer, it will rapidly oxide forming Cu2O when exposed to air. When Ni is subsequently plated over this oxide layer, it will adhere very poorly to the underlying Ni. As soon as any stress is applied, the interface will delaminate and a blister will form.
In this article, we have taken a failure analysis approach to describing a number of assembly related issues that are directly linked to contamination in the plating process. We have considered the impact of organic contamination and metallic contamination on wirebond reliability, the impact of nodule formation on die attach void formation, the impact of “black pad” formation on solder wetting, the impact of Pd in the plating sequence on die attach void formation and discussed how plating bath impurities can result in metal delamination (blister formation) during die attach. For each of these defects, we have shown failure analysis data to support the failure mechanism, and also suggested how each may be mitigated by changes in process or control.
1. C.W. Horsting, 10th Annual Proc. IEEE, Reliability Physics Symp. Las Vegas, Nevada 1972 pp 155-158
2. George Harman, “Wire Bonding in Microelectronics Materials, Processes, Reliability and Yield, McGraw-Hill, 1997 p173
3. George Harman, “Wire Bonding in Microelectronics Materials, Processes, Reliability and Yield, McGraw-Hill, 1997 p174
Dr. Jonathan Harris has played a leadership role in development and characterization of advanced materials for electronics applications for 20 years. Dr. Harris is the President of CMC Laboratories, a failure analysis laboratory that focusses on advanced materials in LED, medical electronics, power electronics, automotive and military applications. Dr. Harris has a PhD in Solid State Physics from Brown University.