Betting On Wafer-Level Fan-Outs
Chipmakers focus on packaging to reduce routing issues at 10nm, 7nm. Tool and methodology gaps remain.
Advanced packaging is starting to gain traction as a commercially viable business model rather than just one more possible option, propelled by the technical difficulties in routing signals at 10nm and 7nm and skyrocketing costs of device scaling on a single die.
The inclusion of a fan-out package for logic in Apple’s iPhone 7, based on TSMC’s Integrated Fan-Out (InFO) technology, has garnered most of the headlines in this space, but there is much more happening in this market. Even within the iPhone 7, there are 43 other wafer-level packages on the main PCB, plus wafer-level packages in the Lightning cable and earbuds, according to Jan Vardaman, president of TechSearch International. She noted that Hisilicon and MediaTek are expected to follow with their own application processor packaging. Others, such as Oppo and Vivo, China’s top two smart phone makers, already are using some version of advanced packaging, as well.
“There is a continued proliferation of packages,” Vardaman said. “The big discussion now is about heterogeneous integration. The problem is that phone boards are running out of space, so they need to come up with a way to minimize the package footprint.”
Fan-out wafer-level packaging has emerged as the top choice in the mobile market after nearly a decade of behind-the-scenes work. One reason it took so long is that this wasn’t a top priority for chipmakers as long as device scaling was possible. But it also proved harder than anyone initially thought.
Fan-outs are less expensive than 2.5D, because there is no interposer. 2.5D remains the top choice for high-performance applications, such as networking or server chips, because the through-silicon vias in the interposer can move signals more quickly than other interconnects. Still, performance differences between the two are narrowing.
“We expect that high-density fan-outs will have similar performance as high-density 2.5D, but it will take time,” said William Chen, ASE fellow and senior technical advisor. “Until then, the emergence of fan-out will push 2.5D more to higher-end applications.”
What is fan-out wafer-level packaging?
Over the years, packaging has evolved using several technologies. Packages based on wirebond techniques have been employed for decades to extend tight leads, and that concept was extended using flip-chip packaging.
In contrast, FO-WLP combines multiple chips into a single package, eliminating the routing congestion while also enabling the benefits of feature shrinks for digital logic. This is particularly important in smart phones because it requires less area, which in turn allows for a thinner phone. Active and passive elements in a chip can be moved very close to each other, using shorter and faster connections than is possible on a single die, with fewer parasitics.
Fan-outs are not a new concept. What’s new is the wafer-level packaging approach. Individual die typically are either embedded into a mold compound or attached to a wafer and then under-filled. From there, a redistribution layer (RDL) is developed using physical vapor deposition to route I/O connections, a dielectric film is added for insulation, and copper bumps or pillars are added.
The exact order of those steps can vary depending upon the approach, but the key variables here are yield and reliability. Yield can be affected by mechanical stress, which can cause warpage, delamination in the RDL, and in some cases cracking or separation from the solder balls. Reliability is a measure of how that package performs over time, and that typically takes years to understand and fine-tune.
FO-WLP is considered a middle-ground solution between 2.5D and organic substrate system-in-package in terms of lines and spaces. Several industry sources say Apple’s iPhone uses three layers with 5-5µm, 10-10m and 10-10µm lines-spaces in the RDL. High-density versions are under development for 5-5µm on every layer. STATS ChipPAC and Qualcomm began joint development of a 2-2µm project.
The first generation of fan-outs was based on Infineon’s embedded wafer-level ball grid array (eWLB), which was introduced in 2009. Freescale (now NXP) followed that in 2012 with redistributed chip packaging (RCP). More recently, Amkor has added silicon-less integrated module (SLIM) and silicon wafer integrated fan-out technology (SWIFT). There are numerous other slices of this approach, as well.
“There were 50 types of chip-scale packaging,” said Seung Wook (S.W.) Yoon, director of product technology marketing at STATS ChipPAC. “Of those, 20 were wafer-level packaging.”
Each is unique in some way, too. “It’s not easy to standardize a package format or structure,” Yoon said. “The major concern from chip designers, and even foundries, is that in a package the electrical issues, parasitics and RC are all different. This means you have to consider system integration at the system level, and work with the customer to develop a SPICE model and a package model. If the layers change, the parasitics in the materials change.”
Yield and test issues
The sources of yield and quality issues aren’t always obvious, though. Unlike an ASIC or SoC, all of the pieces aren’t necessarily manufactured on the same wafer or even using the same process technology.
“The big challenge we’re seeing is quality management,” said David Park, vice president of worldwide marketing at Optimal Plus. “In effect, you may have a good die in a bad neighborhood. When you develop a reconstituted wafer for a fan-out wafer-level package, your die can come from any number of other wafers. You need to be able to correlate that reconstituted wafer back to the original silicon wafer to determine if there was a bad area of the original silicon wafer. Right now, that’s tricky because there is no one-to-one correlation of the source silicon to the reconstituted wafer.”
Park said that could require data from as many as 15 different wafers. “You can still do a parametric test, but wafer sort has become final test for these packages. You need a more comprehensive approach. With fan-out wafer-level packaging, you get all the cost benefits of scaling and all the manufacturing benefits, but you can lose good quality control because of geographic issues.”
That, in turn, can affect time-to-market. Expectations are that in the near future developing devices using fan-out wafer level packaging will take less time than building an SoC and integrating all of the components on a single die, and ultimately it will be lower cost. The ultimate goal is to have a marketplace of well-characterized and tested chiplets, developed at whatever process node makes sense for those technologies and for a particular application.
“Eventually, you will be able to pick from a menu,” said ASE’s Chen. “But right now we have to develop design tools. If you have a good set of design tools, that’s a first step to standardization. From my standpoint, that will be an important step.”
That point has not been lost on EDA companies, which are busy developing solutions to fill in the gaps in tool flows and design methodologies.
“What’s missing is the ability to perfect and tune up the implementation,” said Keith Felton, IC packaging product marketing manager in Mentor Graphics’ Board Systems Division. “All the [PCB] tools have been brought up assuming there is an organic substrate, so you have PCB constraints and rule sets. Those are fairly sloppy compared to what’s available for a chip, which is very strict about how metal structures can be manufactured.”
That requires both an extension to process design kits (PDKs) and an understanding of how a more rigorous fabrication will impact final design.
“We also need a process of signoff on different levels, because this is an expensive fabrication process,” Felton said. “You have lots of masks, and you need to validate everything. But there is not a lot of tweaking you can do and still maintain the price point necessary to make this work. At the same time, you need an environment where you can build a prototype and bring different blocks together to build a package. You may want processors side-by-side with the memory stack or above them. You can have thousands of blocks in these packages, but you cannot have that many metal layers because you have to figure out where to place critical signal buses. And then you have to do timing analysis, and you need a lot of early prototyping for all of this. This has never happened before in this segment. In the past, you would build a package and throw things together. So now you need to implement design rules, not a bunch of what-if scenarios. That means companies need to spend more time up front to determine how to construct multiple die inside a package before they commit to a physical detailed design. That will shorten the time, make it more robust, but still allow you to explore as many variants as possible.”
Also under development is a methodology that adds consistency for power, signal integrity, electrostatic discharge and thermal analysis. ANSYS is working with large OSATs and foundries on a FO-WLP flow that addresses all of those, according to Aveek Sarkar, ANSYS’ vice president of product engineering and support.
“What we’re working on now is a way to replicate everything through GDS or multi-chip modules,” Sarkar said. “These are the steps to follow. And even in GDS, we will add an extra layer of granularity. The focus is more on methodology on how to deal with power, thermal, mechanical stress, warpage, as well as a series of handoffs from the chip level to the package level to the system level.”
Future directions and issues
Because of the small form factor, the bulk of the vast majority of FO-WLP implementations have been for the mobile market. Most companies expect the market to become much more diverse, including a mix of new applications and as a way of reducing the cost for 10/7nm SoCs and adding in much more flexibility.
“Now it’s starting to move to more integrated solutions like baseband and RF and LIDAR sensors,” said STATS ChipPAC’s Yoon. “You can do this with a stacked die in 3D. FO-WLP is one way to enable that without TSVs. With WLP, the copper layer is very smooth so you get better performance. There is no dielectric loss in high frequency.”
The keys here will be yield and cost, and if yield can be improved and cost lowered, the number of markets served by this technology could expand quickly.
“You need very good yield,” said ASE’s Chen. “Otherwise you lose. We believe that requires a chip-first process. It also will have to be thinner than what is available today. That will be very important as this technology rolls out and people are using different kinds of fan out. We will see how those roll out. We are working on making the lines and spaces more tolerant so we get better yield.”
Cost is another key factor in packaging, and one that has stymied the widespread adoption of 2.5D. The cost of a silicon interposer is the culprit, which is why companies such as eSilicon and Samsung currently are developing organic interposers. The organic interposers also are flexible, which makes them less prone to stress effects.
While the packaging and equipment industries have taken packaging very seriously, most of the rest of the chip world is just beginning to embrace it. Some of that is due to thermal and physical effects at 10nm and 7nm, challenges in routing and the effect on signal integrity, and the overall rising cost of dealing with those issues. Some of it also is due to the fragmentation of end markets, particularly as more devices are connected to the Internet, and the need for much more customized solutions in lower volume. That plays well into a platform approach, where a 7nm logic chip can be paired with an analog chip in the same package, or in multiple packages packed together more tightly on a board.
But fully understanding tradeoffs from all the possible permutations, doing that quickly enough, and ensuring good yield from what amounts to more customized electronics that includes everything from up-front architectural design to final packaging and test, still has a way to go. Progress is being made on all fronts, but the number of options and nuances is daunting.
“This is like being given a 3D jigsaw puzzle and you have to figure out where to place each piece,” said Mentor’s Felton. “It requires a big left shift for more rapid evaluation—with enough accuracy to look at how to connect the dots—and you need to be able to visualize and design in 3D, which is an alien concept to most chip designers. If not, there is a large chance you will have to re-spin the design.”
By: Ed Sperling