Signal Integrity and Intersymbol Interference (ISI) for 10 – 56Gbpsec Jitter Analysis
I am only recently recovering from attending DesignCon (Wild River Technology); a very full week working in our booth, meeting old friends, and co-presenting a well-received tutorial on “32 to 56Gbps Serial Link Analysis and Optimization Methods for Pathological Channels“, which included co-authors from Keysight Technology and Xilinx. The concept:
The essential underlining concept of pathological channels testing is you use pristine signal integrity test platforms to build pathologies or issues such as loss, resonance, or crosstalk in a methodical and systemic way. The “pathology” is an isolated issue (or issues) that generates a precise challenge for optimizing the channel in a systematic fashion. You build the structures up using WRT phase stable cables (<20degrees to 50GHz).
Two platforms were used as pathological channels for the Xilinx Ultra Scale+ FPGA: ISI-32 and XTALK-32 (see picture).
I hear some engineers voice their opinion on our ISI-32 Platform (see left) that “It is only loss. I can easily build that! We already have something we built 10 years ago that serves that purpose”.
This platform is not simple to design and fabricate:
Getting precise and clean ISI is really hard to do for 10-56Gbpsec.
For example, the launch design needs to be pristine to maintain return loss or you’re not testing for loss, but instead reflected energy off the ports. The new IEEE PG370 TG1 specification deals with return loss versus loss margin. -10dB return loss S11 margin at 40 GHz is very tough to achieve, with many hours of simulation time using Simbeor required to optimize the launch for stellar signal integrity. Secondly, weave issues add periodicity and group delay noise to the forward transmission, which shows up as resonance in the system, which in turn wreaks havoc with ISI repeatability. We use very homogenous moderate loss material with a select and expensive pc vendor who spreads the weave in X-Y direction, then we layout our structures off horizontal axis to mitigiate weave even further – the objective is pure dielectric and conductive losses. Finally, we found if the pc board is too thin it flexes and you get dramatic changes in forward transmission SDD21, and return loss SDD11, which creates jitter analysis measurement non-repeatability – so we increased the stack-up thickness just to make the platform rigid.
We also developed a nifty ADS Serial Link Test suite that we provide that has IBIS-AMI capabiilty and all the S-parameters (ask us for a demo). The tutorial represented a culmination of 2 years of work for improving serial link characterization methods, we were really happy how it played out and found DesignCon to have really great energy this year! See WRT website “resources- papers” for a copy of the tutorial.