Ultra-low ESL and Ultra-low Profile Silicon Capacitor interest in decoupling high-speed IC

Abstract — Decoupling power supply of high-speed IC is becoming more and more challenging. In that perspective, Ultra-low Equivalent Series Inductance (ESL) is a key factor for efficient decoupling capacitors. Reducing the parasitic due to the assembly is another important goal that can be achieved through ultra-low thickness. Thirdly, high stability maintains effective capacitance regardless of biasing conditions.

 Keywords — ultra-low ESL capacitor; ultra-low profile; silicon capacitor; PICS technology; high-speed IC; decoupling capacitors; high stability; land-side capacitor; BGA package

I. Introduction

Powering high-speed IC and smartphone application processors is becoming more and more challenging. Indeed, the evolution of process nodes induces lower operating voltage and higher working frequencies.

This leads to the need for more efficient decoupling capacitors providing low profile and high performances.

 

II. Main parameters of a decoupling capacitor

A. Capacitance, ESR and ESL

The role of the decoupling capacitor is twofold: suppress the noise from the power supply and act as power reservoir when the IC is drawing a large amount of current. A measure of the capacitor efficiency is its impedance: the lower the impedance, the more efficient the capacitor.

 

The non-ideal behavior of a capacitor is generally modeled [1] by a capacitor, an Equivalent Series Resistance (ESR) and an Equivalent Series Inductance (ESL) in series as shown in figure 1.

Figure 1: Electrical model of a capacitor C, ESL, ESR.

 

The impedance magnitude of this model is given as [1]:

Eq. 1 shows that, at high-frequencies, ESL becomes the main contributor to the impedance, minimizing the ability of the capacitor to maintain a low impedance.

 

 

Figure 2: Impedance magnitude of a capacitor model C, ESL, ESR.

The figure 2 shows a graph of impedance magnitude against frequency.

  • At low frequencies, the impedance depends mainly on the capacitive term.
  • At the self-resonance frequency, the capacitance and ESL values cancel each other out. The impedance is due to the ESR parasitic.
  • At high frequencies, the impedance depends mainly on the ESL.

III. Benefits of ultra-low profile

The request for ultra-low profile capacitors is mainly driven by consumers eager for ultra-thin portable devices. Furthermore, integrating decoupling capacitors in the IC package reduces the inductive and resistive parasitic effects due to routing.

To meet this demand for ultra-low profile capacitors, IPDiA developed the PICS3HD node which combines high-density (500 nF/mm²) with low thickness (100 µm). Table 1 shows IPDiA’s ultra-low profile roadmap.

 

Table 1: IPDiA’s low-profile Silicon Capacitor roadmap

Figure 3 shows 2 typical assemblies of capacitors in a conventional BGA Package-on-Package (PoP).

 

Figure 3: PoP BGA package cross section

  • Die Side: the capacitor is placed side by side with the active-die. Space is limited by the size of the processor die and the peripheral connections between the bottom laminate and the top package containing memory dies.
  • Land Side: the capacitor is placed between the BGA balls. Achieving high capacitance density is very important to limit the number of BGA balls de-populated.

The ultra-low profile of silicon capacitors allows a package height reduction for both die-side and land-side assemblies. The latest evolutions in the silicon capacitor roadmap address the Wafer Level Packaging (WLP) technologies that require 50 µm to 70 µm thick capacitors.

IV. Benefits of Ultra-low ESL

A. Mosaïc design

ESL depends mainly on the area of the current loop. It can therefore be improved through an optimized layout. In that perspective, IPDiA developed an architecture called MOSAIC that reduces the parasitic of the capacitors (ESR and ESL) [2] [3] through the parallelization of elementary capacitive cells presented in figure 4.

 

Figure 4: Mosaic design

Figure 5: Picture of UESL 0404 470 nF silicon capacitor

The MOSAIC architecture can be combined with high density PICS3HD node (see Table 1) in standalone silicon capacitors as depicted in figure 5.

 

B. Impedance of Ultra-low ESL silicon capacitor

MOSAIC architecture can achieve an ESL as low as 10 pH, like the UESL 0404 470 nF silicon capacitor. Such Ultra-low ESL maintains a low impedance over a large frequency range, as displayed in figure 6.

Figure 6: Impedance magnitudes vs frequency of IPDiA UESL 0404 470 nF and standard MLCC solution

Ultra-low ESL of 10 pH improves power supply decoupling performance by more than 40 dB measured at 1.3 GHz compared with the standard solution.

 

V. Benefits of High stability

A. DC voltage biasing

The dielectric materials used to manufacture the capacitor have an important impact on stability over DC biasing [2]. A silicon capacitor using oxy-nitride composites, like PICS3HD, features high stability over DC biasing voltage (capacitance variation remains <0.5 % over the operating voltage range).

Figure 7 compares the capacitance variations over DC voltage biasing of the oxy-nitride silicon based capacitor and other standard types of MLCC technologies.

 

Figure 7: Capacitance derating over DC voltage biasing of various capacitor technologies

B. Temperature derating

A similar comparison is performed with respect to temperature derating in figure 8. PICS3HD capacitance temperature variation is +/- 100 ppm/°C. However, X5R capacitors have, by definition [4], a maximum of 15 % derating over the temperature operating range.

Figure 8: Capacitance derating over temperature for various capacitor technologies

C. Aging

Class II (ferroelectric) dielectric, including X5R type, are subject to a phenomenon of capacitance decay over time, called the “aging effect”. This derating is logarithmic and typically several percent per decade hour. As PICS3HD is a non-ferroelectric material, the aging effect is negligeable (capacitance change < 0.001 % after 10 000 h).

 D. Comparison of effective capacitance

The deratings mentioned above have a significant impact on the performance of the capacitors.

Table 2: Comparison of derating for IPDiA UESL 0404 470 nF and conventional 1 μF X5R 4 VDC MLCC

Table 2 shows that the effective capacitance of a MLCC 1 µF X5R 4 V rated voltage MLCC under 1.8 V, 85 °C and after 10 000 hours of operating is more than halved compared with the nominal capacitance.

A 470 nF silicon capacitor therefore has same effective capacitance as a 1 µF MLCC under biasing conditions.

 

VI. Conclusion

IPDiA capacitors offer simultaneously low profile, low ESL and high effective capacitance. Ultra-low ESL and ultra-low profile characteristics make silicon capacitors a good alternative for effective decoupling of high-speed IC and smartphone application processors.

 

References

[1]    Y. Chase, “Introduction to choosing MLC capacitors for bypass/decoupling applications” AVX Corporation, Myrtle Beach, SC.

[2]    F.Voiron and L.Fourneaud, “Silicon high-density capacitors for power decoupling applications” IEEE International Workshop on Integrated Power Packaging, May 3rd to May 6th 2015, Chicago, IL,USA

[3]    M.Jatlaoui,L.Fourneaud,F.Voiron, “New ultra low ESR Mosaic PICS capacitors for power conversion” European Microwave Integrated Circuits Conference, September 6th to September 11th 2015, Paris, France

[4]    EIA-198-C Standard, Ceramic Dielectric Capacitors Classes I, II, III and IV, Electronic Components Industry Association, Nov-83

 

by Frédéric Nodet

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