JTAG Technologies – 25 Years of Innovation and Dedication to Boundary Scan

electronica 2018 – Hall A3.221

This year (2018) JTAG Technologies are proud to celebrate their 25th year of developing, supplying and supporting world-class board (PCBA) test and programming solutions based on IEEE Std 1149.x .
During this period there have been a great many technological advancements not only within our niche area of board test and programming but also throughout the sectors of Aerospace, Automotive, Defence, Telecoms and Datacoms where many of our customers operate. Meanwhile the world’s manufacturing centres have moved frequently providing fresh supply challenges every few years. .JTAG Technologies however have always remained at the forefront of JTAG (boundary-, scan), IEEE Std.1149.x developments.
With all product development, marketing and sales activities supported in house JTAG Technologies has been uniquely positioned as the world’s most focussed supplier of test and programming solutions for design and production professionals alike.
In fact since the launch of the company JTAG Technologies has been responsible for remarkable number of industry firsts, for example:
1994 – first ATPG (Automatic Test Program Generator)system for developing memory cluster tests
1995 – first universal in-system programming solution for CPLDs
1997 – first controller with dedicated ‘memory behind the pin’ for high-speed flash programming and testing – The JT 3710 ‘DataBlaster’
2009 – first free-for-life boundary-scan utility tool – JTAGLive (Buzz)
2011 – first low-cost emulative test solutions based on processor core control – ‘CoreCommander

While there has been inevitable changes in market conditions throughout this 25 year period JTAG Technologies’ consistent and determined approach to the important aspects of the business, namely world-wide customer support and continuous product development have meant that JTAG Technologies have always been able to offer a first class product and service whenever and wherever it is needed.

At this year’s electronica 2018 in Munich we are happy to present you the following
enhanced products and features:

• The latest version of its acclaimed Visualizer graphical viewing tool for board (PCB) layouts and schematics. Allowing users to assess fault coverage data and pin-point production test faults in a snap.

Wide-ranging CAD support
With its wide range of CAD (EDA) tool import filters Visualizer is the number one choice for professional boundary-scan development and test engineers. Users can import schematic data direct from Mentor (Pads, DxDesigner, Capture) Cadence, Altium and Zuken tools as well as board layout information in ODB++ and a dozen other vendor specific formats.

• JTAG Maps
Introduced in this version of Visualizer, the new Maps feature offers a basic test-accessibility view by a simple click of the mouse. The view can easily be fine-tuned by adding just a few key component descriptions to a look up table. What’s more using customisable colours to indicate test coverage levels or access types, a colour-coded schematic can be displayed or printed. Once the design has been optimized for boundary-scan test coverage and committed to layout, final application development can begin in the JTAG ProVision developer tool.

• CoreCommander Device control via internal JTAG access – processor and FPGA cores
While many ICs are equipped with a JTAG (IEEE Std. 1149.1) boundary-scan register (BSR), a significant number of microprocessors and DSPs can be found with deficient or even non-existent BSRs. CoreCommander Micro uses the on-chip debug mode of processors to access ports and embedded peripheral controllers to promote ‘kernel-centric’ testing. Similarly, in the case of today’s Field Programmable Gate Arrays (FPGAs) test engineers can ‘bridge’ from the JTAG interface to the resources of the gate array itself. Our CoreCommander FPGA product implements a translator interface that allows our JTAG hardware to control embedded IP cores via a variety of bus interfaces (e.g. Wishbone Avalon etc.).

CoreCommander routines take control of key processor core (e.g. ARM, PPC, X-scale, Cortex etc.) functions using the built-in emulation/debug functions found in today’s RISC and DSP cores. They have been developed to speed-up board testing and debug by enabling kernel-centric testing. CoreCommander offer two modes of operation:
• Interactive – offering direct control of the core or;
• Python embedded – where controls can be scripted into a complete program.

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